1. Field of the Invention
The invention relates to a non-volatile semiconductor memory device, such as an NAND flash memory, and further relates to a programming verification method.
2. Description of Related Art
An NAND flash memory includes a plurality of NAND strings, and one NAND string includes: a plurality of memory cells connected in series; a source line side selection transistor connected with one end of the memory cell; and a bit line side selection transistor connected with the other end of the memory cell. A control gate of each memory cell is connected with the corresponding word line. A gate of the source line side selection transistor is connected with a selection gate line SGS, and a gate of the bit line side selection transistor is connected with a selection gate line SGD. A plurality of the NAND strings are formed in a P well along a row direction, and one P well constitutes a block of a memory cell array.
The memory cell has an NMOS structure, which includes: a floating gate (charge storage layer) formed to be separated by a tunnel oxide layer; and a control gate formed above the floating gate with a dielectric layer therebetween. When electrons accumulated in the floating gate, a threshold value of the memory cell shifts in the positive direction, and this state is generally called data “0”. On the other hand, when the electrons are released from the floating gate, the threshold value shifts to 0 or in the negative direction, and this state is called data “1”. FIG. 1 illustrates the distribution widths of the threshold values of the data “0” and “1” of the memory cell, wherein the programming or erasing is controlled by maintaining the threshold value of the memory cell within the distribution width.
In the tunnel oxide layer or the floating gate of the memory cell, errors may occur due to parameter variation of the manufacturing process or time variation. Thus, all the memory cells may not be uniform. That is to say, while some memory cells may be easy to inject electrons, some memory cells may be difficult to inject electrons. Even if these memory cells are applied with the same programming voltage, their threshold values may have different shift amounts. For this reason, the following situation may occur. That is, one memory cell may reach the threshold value distribution width of “0” immediately while another memory cell does not reach the threshold value distribution width of “0” immediately.
To cope with this situation, control is usually performed by programming verification, so as to apply the programming voltage again to the memory cell with insufficient electron injection to make the threshold value of the memory cell fall within the distribution width of “0”.
Patent Literature 1 discloses a programming method for narrowing the distribution width of the threshold value of the memory cell and performing high-speed electron injection. As shown in FIG. 2, the programming method divides the programming voltage into a plurality of pulses and thereby applies the programming voltage to the control gate of the memory cell. The initial programming voltage applied to the control gate has a peak value Vpgm, and the peak value of the pulse gradually increases by AVpp. The pulse is a fixed time, and a maximum shift amount ΔVth of the threshold value of the memory cell in one electron injection is equal to ΔVpp. Moreover, Patent Literature 2 discloses a programming method, which divides the programming pulse voltage into a low voltage width portion and a high voltage width portion to suppress the influence of over shoot voltage considering that it is difficult to accurately control the shift amount of the threshold value due to the over shoot of the programming pulse voltage.